Junior AMS Verification Engineer

Role Summary:

• Develop SV Real number and Verilog-AMS models for analog blocks
• Find design bugs/issues in Architecture/design of Analog/Mixed Signal IPs in terms of functional verification, robustness checks with latest verification methodologies
• Top level Analysis & verification of test-modes & DFT strategy for analog blocks.

Job Qualification:

• Master’s Degree in Electronics, Electrical Engineering or Computer science.
• PhD is a plus.
• Knowledge in Verilog, System Verilog, Verilog-AMS and/or Verilog-A
• 6+ months experience in Analog Mixed Signal design/verification is a plus.
• English (read, spoken, written) is a must.

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